ports/cad/verilator/files/patch-src-verilog.y
Sunpoet Po-Chuan Hsieh becaac537e Fix build with bison 3.7.4
PR:		248911
Exp-run by:	antoine
2021-01-26 13:59:25 +00:00

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--- src/verilog.y.orig 2020-08-14 11:38:09 UTC
+++ src/verilog.y
@@ -31,7 +31,6 @@
#include <cstdarg>
#include <stack>
-#define YYERROR_VERBOSE 1 // For prior to Bison 3.6
#define YYINITDEPTH 10000 // Older bisons ignore YYMAXDEPTH
#define YYMAXDEPTH 10000