mirror of
https://git.freebsd.org/ports.git
synced 2025-06-30 00:50:29 -04:00
be8438731c
- emulators/riscv-fesvr, RISC-V Frontend Server - emulators/riscv-isa-sim, Spike, a RISC-V ISA Simulator Original work is done by sbruno Reviewed by: br (earlier version) Differential Revision: https://reviews.freebsd.org/D7527
10 lines
257 B
C++
10 lines
257 B
C++
--- riscv/insn_template.cc.orig 2016-08-01 15:40:47 UTC
|
|
+++ riscv/insn_template.cc
|
|
@@ -1,6 +1,6 @@
|
|
// See LICENSE for license details.
|
|
|
|
-#include "insn_template.h"
|
|
+#include "insn_template.hpp"
|
|
|
|
reg_t rv32_NAME(processor_t* p, insn_t insn, reg_t pc)
|
|
{
|