mirror of
https://git.freebsd.org/ports.git
synced 2025-06-24 14:10:30 -04:00
a0a4302b7e
- Corrected some of the old ones which appeared to have been originally typed wrong. PR: 138129
684 lines
22 KiB
C
684 lines
22 KiB
C
--- cpuid.c.orig 2002-01-02 15:14:51.000000000 +0900
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+++ cpuid.c 2009-08-26 14:08:07.000000000 +0900
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@@ -3,14 +3,17 @@
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* Updated 24 Apr 2001 to latest Intel CPUID spec
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* Updated 22 Dec 2001 to decode Intel flag 28, hyper threading
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* Updated 1 Jan 2002 to cover AMD Duron, Athlon
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+ * Updated 24 Aug 2009 to decode additional Intel flags
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* May be used under the terms of the GNU Public License (GPL)
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* Reference documents:
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- * ftp://download.intel.com/design/pro/applnots/24161809.pdf (AP-485)
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+ * http://www.intel.com/Assets/PDF/appnote/241618.pdf (AP-485 August 2009)
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* http://developer.intel.com/design/Pentium4/manuals/24547103.pdf
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* http://developer.intel.com/design/pentiumiii/applnots/24512501.pdf (AP-909)
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* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/20734.pdf
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- *
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+ * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
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+ * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25481.pdf
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+ *
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*/
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#include <stdio.h>
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@@ -20,17 +23,34 @@
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void dointel(int),doamd(int),docyrix(int);
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void printregs(int eax,int ebx,int ecx,int edx);
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-#define MAXBRANDS 9
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+#define MAXBRANDS 24
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char *Brands[MAXBRANDS] = {
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- "brand 0",
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+ NULL,
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"Celeron processor",
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"Pentium III processor",
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"Intel Pentium III Xeon processor",
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- "brand 4",
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- "brand 5",
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- "brand 6",
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- "brand 7",
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+ "Intel Pentium III processor",
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+ NULL,
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+ "Mobile Intel Pentium III processor-M",
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+ "Mobile Intel Celeron processor",
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+ /* 8 */
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"Intel Pentium 4 processor",
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+ "Intel Pentium 4 processor",
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+ "Intel Celeron processor",
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+ "Intel Xeon processor",
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+ "Intel Xeon processor MP",
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+ NULL,
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+ "Mobile Intel Pentium 4 processor-M",
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+ "Mobile Intel Celeron processor",
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+ /* 16 */
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+ NULL,
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+ "Mobile Genuine Intel processor",
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+ "Intel Celeron M processor",
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+ "Mobile Intel Celeron processor",
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+ "Intel Celeron processor",
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+ "Mobile Genuine Intel processor",
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+ "Intel Pentium M processor",
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+ "Mobile Intel Celeron processor",
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};
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#define cpuid(in,a,b,c,d)\
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@@ -89,7 +109,7 @@
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exit(0);
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}
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-char *Intel_feature_flags[] = {
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+char *Intel_feature_flags[32] = {
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"FPU Floating Point Unit",
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"VME Virtual 8086 Mode Enhancements",
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"DE Debugging Extensions",
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@@ -124,6 +144,60 @@
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"31 reserved",
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};
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+char *Intel_feature_flags2[32] = {
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+ "SSE3 SSE3 extensions",
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+ "PCLMULDQ PCLMULDQ instruction",
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+ "DTES64 64-bit debug store",
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+ "MONITOR MONITOR/MWAIT instructions",
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+ "DS-CPL CPL Qualified Debug Store",
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+ "VMX Virtual Machine Extensions",
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+ "SMX Safer Mode Extension",
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+ "EST Enhanced Intel SpeedStep Technology",
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+ "TM2 Thermal Monitor 2",
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+ "SSSE3 Supplemental Streaming SIMD Extension 3",
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+ "CNXT-ID L1 Context ID",
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+ NULL,
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+ NULL,
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+ "CX16 CMPXCHG16B",
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+ "xTPR Send Task Priority messages",
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+ "PDCM Perfmon and debug capability",
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+ NULL,
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+ NULL,
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+ "DCA Direct Cache Access",
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+ "SSE4.1 Streaming SIMD Extension 4.1",
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+ "SSE4.1 Streaming SIMD Extension 4.2",
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+ "x2APIC Extended xAPIC support",
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+ "MOVBE MOVBE instruction",
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+ "POPCNT POPCNT instruction",
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+ NULL,
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+ "AES AES Instruction",
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+ "XSAVE XSAVE/XSTOR states",
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+ "OSXSAVE OS-enabled extended state managerment",
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+ NULL, NULL, NULL, NULL
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+};
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+
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+char *Intel_ext_feature_flags[32] = {
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+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL,
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+ "SYSCALL SYSCALL/SYSRET instructions",
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ "XD-bit Execution Disable bit",
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+ NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL, NULL,
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+ "EM64T Intel Extended Memory 64 Technology",
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+ NULL, NULL
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+};
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+
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+char *Intel_ext_feature_flags2[32] = {
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+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ "LAHF LAHF/SAHF available in IA-32e mode",
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+ NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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+};
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+
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/* Intel-specific information */
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void dointel(int maxi){
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printf("Intel-specific functions:\n");
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@@ -131,12 +205,15 @@
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if(maxi >= 1){
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/* Family/model/type etc */
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int clf,apic_id,feature_flags;
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+ int feature_flags2 = 0;
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+ int ext_feature_flags = 0;
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+ int ext_feature_flags2 = 0;
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int extended_model = -1,extended_family = -1;
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- unsigned long eax,ebx,edx,unused;
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+ unsigned long eax,ebx,ecx,edx;
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int stepping,model,family,type,reserved,brand,siblings;
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int i;
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- cpuid(1,eax,ebx,unused,edx);
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+ cpuid(1,eax,ebx,ecx,edx);
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printf("Version %08lx:\n",eax);
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stepping = eax & 0xf;
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model = (eax >> 4) & 0xf;
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@@ -147,6 +224,7 @@
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apic_id = (ebx >> 24) & 0xff;
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siblings = (ebx >> 16) & 0xff;
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feature_flags = edx;
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+ feature_flags2 = ecx;
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printf("Type %d - ",type);
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switch(type){
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@@ -253,9 +331,25 @@
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case 8:
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printf("Pentium III/Pentium III Xeon - internal L2 cache");
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break;
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+ case 9:
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+ printf("Intel Pentium M processor model 9");
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+ break;
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+ case 10:
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+ printf("Pentium III Xeon processor model A");
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+ break;
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+ case 11:
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+ printf("Intel Pentium III processor model B");
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+ break;
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+ case 13:
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+ printf("Intel Pentium M processor model D");
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+ break;
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}
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break;
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case 15:
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+ extended_model = (eax >> 16) & 0xf;
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+ if (extended_model == 0) {
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+ printf("Intel Pentium 4 processor (generic) or newer");
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+ }
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break;
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}
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printf("\n");
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@@ -270,16 +364,22 @@
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brand = ebx & 0xff;
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if(brand > 0){
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printf("Brand index: %d [",brand);
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- if(brand < MAXBRANDS){
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+ if(brand < MAXBRANDS && Brands[brand] != NULL){
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printf("%s]\n",Brands[brand]);
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} else {
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printf("not in table]\n");
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}
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}
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- cpuid(0x80000000,eax,ebx,unused,edx);
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+ cpuid(0x80000000,eax,ebx,ecx,edx);
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if(eax & 0x80000000){
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/* Extended feature/signature bits supported */
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int maxe = eax;
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+ if (maxe >= 0x80000001) {
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+ unsigned long eax,ebx,ecx,edx;
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+ cpuid(0x80000001,eax,ebx,ecx,edx);
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+ ext_feature_flags = edx;
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+ ext_feature_flags2 = ecx;
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+ }
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if(maxe >= 0x80000004){
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int i;
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@@ -303,12 +403,48 @@
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printf("Hyper threading siblings: %d\n",siblings);
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}
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- printf("\nFeature flags %08x:\n",feature_flags);
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+ printf("\nFeature flags: %08x:\n",feature_flags);
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for(i=0;i<32;i++){
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if(feature_flags & (1<<i)){
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printf("%s\n",Intel_feature_flags[i]);
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}
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}
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+ if(feature_flags2) {
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+ printf("\nFeature flags set 2: %08x:\n",feature_flags2);
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+ for (i = 0; i < 32; ++i) {
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+ if (feature_flags2 & (1 << i)) {
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+ const char* fn = Intel_feature_flags2[i];
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+ if (fn != NULL)
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+ printf("%s\n", fn);
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+ else
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+ printf("%d - unknown feature\n", i);
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+ }
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+ }
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+ }
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+ if(ext_feature_flags) {
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+ printf("\nExtended feature flags: %08x:\n",ext_feature_flags);
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+ for (i = 0; i < 32; ++i) {
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+ if (ext_feature_flags & (1 << i)) {
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+ const char* fn = Intel_ext_feature_flags[i];
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+ if (fn != NULL)
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+ printf("%s\n", fn);
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+ else
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+ printf("%d - unknown feature\n", i);
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+ }
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+ }
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+ }
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+ if(ext_feature_flags2) {
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+ printf("\nExtended feature flags set 2: %08x:\n",ext_feature_flags2);
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+ for (i = 0; i < 32; ++i) {
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+ if (ext_feature_flags2 & (1 << i)) {
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+ const char* fn = Intel_ext_feature_flags2[i];
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+ if (fn != NULL)
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+ printf("%s\n", fn);
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+ else
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+ printf("%d - unknown feature\n", i);
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+ }
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+ }
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+ }
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printf("\n");
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}
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if(maxi >= 2){
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@@ -396,18 +532,66 @@
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case 0x4:
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printf("Data TLB: 4MB pages, 4-way set assoc, 8 entries\n");
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break;
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+ case 0x5:
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+ printf("Data TLB: 4MB pages, 4-way set assoc, 32 entries\n");
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+ break;
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case 0x6:
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printf("1st-level instruction cache: 8KB, 4-way set assoc, 32 byte line size\n");
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break;
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case 0x8:
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printf("1st-level instruction cache: 16KB, 4-way set assoc, 32 byte line size\n");
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break;
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+ case 0x9:
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+ printf("1st-level instruction cache: 32KB, 4-way set assoc, 64 byte line size\n");
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+ break;
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case 0xa:
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printf("1st-level data cache: 8KB, 2-way set assoc, 32 byte line size\n");
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break;
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case 0xc:
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printf("1st-level data cache: 16KB, 4-way set assoc, 32 byte line size\n");
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break;
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+ case 0xd:
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+ printf("1st-level data cache: 16KB, 4-way set assoc, 64 byte line size, ECC\n");
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+ break;
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+ case 0x21:
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+ printf("256-KB L2 (MLC), 8-way set associative, 64 byte line size\n");
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+ break;
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+ case 0x22:
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+ printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64-byte line size\n");
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+ break;
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+ case 0x23:
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+ printf("3rd-level cache: 1-MB, 8-way set associative, sectored cache, 64-byte line size\n");
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+ break;
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+ case 0x25:
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+ printf("3rd-level cache: 2-MB, 8-way set associative, sectored cache, 64-byte line size\n");
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+ break;
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+ case 0x29:
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+ printf("3rd-level cache: 4-MB, 8-way set associative, sectored cache, 64-byte line size\n");
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+ break;
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+ case 0x2c:
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+ printf("1st-level data cache: 32-KB, 8-way set associative, 64-byte line size\n");
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+ break;
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+ case 0x30:
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+ printf("1st-level instruction cache: 32-KB, 8-way set associative, 64-byte line size\n");
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+ break;
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+ case 0x39:
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+ printf("2nd-level cache: 128-KB, 4-way set associative, sectored cache, 64-byte line size\n");
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+ break;
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+ case 0x3a:
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+ printf("2nd-level cache: 192-KB, 6-way set associative, sectored cache, 64-byte line size\n");
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+ break;
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+ case 0x3b:
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+ printf("2nd-level cache: 128-KB, 2-way set associative, sectored cache, 64-byte line size\n");
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+ break;
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+ case 0x3c:
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+ printf("2nd-level cache: 256-KB, 4-way set associative, sectored cache, 64-byte line size\n");
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+ break;
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+ case 0x3d:
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+ printf("2nd-level cache: 384-KB, 6-way set associative, sectored cache, 64-byte line size\n");
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+ break;
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+ case 0x3e:
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+ printf("2nd-level cache: 512-KB, 4-way set associative, sectored cache, 64-byte line size\n");
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+ break;
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case 0x40:
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printf("No 2nd-level cache, or if 2nd-level cache exists, no 3rd-level cache\n");
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break;
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@@ -426,23 +610,67 @@
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case 0x45:
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printf("2nd-level cache: 2MB, 4-way set assoc, 32 byte line size\n");
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break;
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+ case 0x46:
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+ printf("3rd-level cache: 4MB, 4-way set associative, 64-byte line size\n");
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+ break;
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+ case 0x47:
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+ printf("3rd-level cache: 8MB, 8-way set associative, 64-byte line size\n");
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+ break;
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+ case 0x48:
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+ printf("2nd-level cache: 3MB, 12-way set associative, 64-byte line size, unified on die\n");
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+ break;
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+ case 0x49:
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+ /* TODO The code needs to be slightly restructured so we can check family and model here */
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+ printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon MP, Family 0Fh, Model 06h\n");
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+ printf("OR 2nd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
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+ break;
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+ case 0x4a:
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+ printf("3rd-level cache: 6MB, 12-way set associative, 64-byte line size\n");
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+ break;
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+ case 0x4b:
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+ printf("3rd-level cache: 8MB, 16-way set associative, 64-byte line size\n");
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+ break;
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+ case 0x4c:
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+ printf("3rd-level cache: 12MB, 12-way set associative, 64-byte line size\n");
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+ break;
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+ case 0x4d:
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+ printf("3rd-level cache: 16MB, 16-way set associative, 64-byte line size\n");
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+ break;
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+ case 0x4e:
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+ printf("3rd-level cache: 6MB, 24-way set associative, 64-byte line size\n");
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+ break;
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case 0x50:
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- printf("Instruction TLB: 4KB and 2MB or 4MB pages, 64 entries\n");
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+ printf("Instruction TLB: 4KB, 2MB or 4MB pages, fully assoc., 64 entries\n");
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break;
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case 0x51:
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- printf("Instruction TLB: 4KB and 2MB or 4MB pages, 128 entries\n");
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+ printf("Instruction TLB: 4KB, 2MB or 4MB pages, fully assoc., 128 entries\n");
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break;
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case 0x52:
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- printf("Instruction TLB: 4KB and 2MB or 4MB pages, 256 entries\n");
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+ printf("Instruction TLB: 4KB, 2MB or 4MB pages, fully assoc., 256 entries\n");
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+ break;
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+ case 0x55:
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+ printf("Instruction TLB: 2MB or 4MB pages, fully assoc., 7 entries\n");
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+ break;
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+ case 0x56:
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+ printf("Data TLB: 4MB pages, 4-way set associative, 16 entries\n");
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+ break;
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+ case 0x57:
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+ printf("Data TLB: 4KB pages, 4-way set associative, 16 entries\n");
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+ break;
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+ case 0x5a:
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+ printf("Data TLB: 2MB or 4MB pages, 4-way set associative, 32 entries\n");
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break;
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case 0x5b:
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- printf("Data TLB: 4KB and 4MB pages, 64 entries\n");
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+ printf("Data TLB: 4KB or 4MB pages, fully assoc., 64 entries\n");
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break;
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case 0x5c:
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- printf("Data TLB: 4KB and 4MB pages, 128 entries\n");
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+ printf("Data TLB: 4KB or 4MB pages, fully assoc., 128 entries\n");
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break;
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case 0x5d:
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- printf("Data TLB: 4KB and 4MB pages, 256 entries\n");
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+ printf("Data TLB: 4KB or 4MB pages, fully assoc., 256 entries\n");
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+ break;
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+ case 0x60:
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+ printf("1st-level data cache: 16-KB, 8-way set associative, sectored cache, 64-byte line size\n");
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break;
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case 0x66:
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printf("1st-level data cache: 8KB, 4-way set assoc, 64 byte line size\n");
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@@ -454,25 +682,37 @@
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printf("1st-level data cache: 32KB, 4-way set assoc, 64 byte line size\n");
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break;
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case 0x70:
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- printf("Trace cache: 12K-micro-op, 4-way set assoc\n");
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+ printf("Trace cache: 12K-micro-op, 8-way set assoc\n");
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break;
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case 0x71:
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- printf("Trace cache: 16K-micro-op, 4-way set assoc\n");
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+ printf("Trace cache: 16K-micro-op, 8-way set assoc\n");
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break;
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case 0x72:
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- printf("Trace cache: 32K-micro-op, 4-way set assoc\n");
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+ printf("Trace cache: 32K-micro-op, 8-way set assoc\n");
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+ break;
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+ case 0x73:
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+ printf("Trace cache: 64K-micro-op, 8-way set assoc\n");
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+ break;
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+ case 0x78:
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+ printf("2nd-level cache: 1MB, 4-way set assoc, 64 byte line size\n");
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break;
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case 0x79:
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printf("2nd-level cache: 128KB, 8-way set assoc, sectored, 64 byte line size\n");
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break;
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case 0x7a:
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- printf("2nd-level cache: 256KB, 8-way set assoc, sectored, 64 byte line size\n");
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+ printf("2nd-level cache: 256KB, 8-way set assoc, sectored, 64 byte line size\n");
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break;
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case 0x7b:
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printf("2nd-level cache: 512KB, 8-way set assoc, sectored, 64 byte line size\n");
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break;
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case 0x7c:
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- printf("2nd-level cache: 1MB, 8-way set assoc, sectored, 64 byte line size\n");
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+ printf("2nd-level cache: 1MB, 8-way set assoc, sectored, 64 byte line size\n");
|
|
+ break;
|
|
+ case 0x7d:
|
|
+ printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
|
|
+ break;
|
|
+ case 0x7f:
|
|
+ printf("2nd-level cache: 512KB, 2-way set assoc, 64 byte line size\n");
|
|
break;
|
|
case 0x82:
|
|
printf("2nd-level cache: 256KB, 8-way set assoc, 32 byte line size\n");
|
|
@@ -486,44 +726,189 @@
|
|
case 0x85:
|
|
printf("2nd-level cache: 2MB, 8-way set assoc, 32 byte line size\n");
|
|
break;
|
|
+ case 0x86:
|
|
+ printf("2nd-level cache: 512KB, 4-way set assoc, 64 byte line size\n");
|
|
+ break;
|
|
+ case 0x87:
|
|
+ printf("2nd-level cache: 1MB, 8-way set assoc, 64 byte line size\n");
|
|
+ break;
|
|
+ case 0xB0:
|
|
+ printf("Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries\n");
|
|
+ break;
|
|
+ case 0xB1:
|
|
+ printf("Instruction TLB: 2MB Pages (8 entries) or 4MB pages (4 entries), 4-way set associative\n");
|
|
+ break;
|
|
+ case 0xB2:
|
|
+ printf("Instruction TLB: 4-KB Pages, 4-way set associative, 64 entries\n");
|
|
+ break;
|
|
+ case 0xB3:
|
|
+ printf("Data TLB: 4-KB Pages, 4-way set associative, 128 entries\n");
|
|
+ break;
|
|
+ case 0xB4:
|
|
+ printf("Data TLB: 4-KB Pages, 4-way set associative, 256 entries\n");
|
|
+ break;
|
|
+ case 0xCA:
|
|
+ printf("Shared 2nd-level TLB: 4-KB Pages, 4-way set associative, 512 entries\n");
|
|
+ break;
|
|
+ case 0xD0:
|
|
+ printf("3rd-level cache: 512KB, 4-way set associative, 64-byte line size\n");
|
|
+ break;
|
|
+ case 0xD1:
|
|
+ printf("3rd-level cache: 1MB, 4-way set associative, 64-byte line size\n");
|
|
+ break;
|
|
+ case 0xD2:
|
|
+ printf("3rd-level cache: 2MB, 4-way set associative, 64-byte line size\n");
|
|
+ break;
|
|
+ case 0xD6:
|
|
+ printf("3rd-level cache: 1MB, 8-way set associative, 64-byte line size\n");
|
|
+ break;
|
|
+ case 0xD7:
|
|
+ printf("3rd-level cache: 2MB, 8-way set associative, 64-byte line size\n");
|
|
+ break;
|
|
+ case 0xD8:
|
|
+ printf("3rd-level cache: 4MB, 8-way set associative, 64-byte line size\n");
|
|
+ break;
|
|
+ case 0xDC:
|
|
+ printf("3rd-level cache: 1.5MB, 12-way set associative, 64-byte line size\n");
|
|
+ break;
|
|
+ case 0xDD:
|
|
+ printf("3rd-level cache: 3MB, 12-way set associative, 64-byte line size\n");
|
|
+ break;
|
|
+ case 0xDE:
|
|
+ printf("3rd-level cache: 6MB, 12-way set associative, 64-byte line size\n");
|
|
+ break;
|
|
+ case 0xE2:
|
|
+ printf("3rd-level cache: 2MB, 16-way set associative, 64-byte line size\n");
|
|
+ break;
|
|
+ case 0xE3:
|
|
+ printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
|
|
+ break;
|
|
+ case 0xE4:
|
|
+ printf("3rd-level cache: 8MB, 16-way set associative, 64-byte line size\n");
|
|
+ break;
|
|
+ case 0xEA:
|
|
+ printf("3rd-level cache: 12MB, 24-way set associative, 64-byte line size\n");
|
|
+ break;
|
|
+ case 0xEB:
|
|
+ printf("3rd-level cache: 18MB, 24-way set associative, 64-byte line size\n");
|
|
+ break;
|
|
+ case 0xEC:
|
|
+ printf("3rd-level cache: 24MB, 24-way set associative, 64-byte line size\n");
|
|
+ break;
|
|
+ case 0xF0:
|
|
+ printf("64-byte prefetching\n");
|
|
+ break;
|
|
+ case 0xF1:
|
|
+ printf("128-byte prefetching\n");
|
|
+ break;
|
|
default:
|
|
printf("unknown TLB/cache descriptor\n");
|
|
break;
|
|
}
|
|
}
|
|
char *AMD_feature_flags[] = {
|
|
- "Floating Point Unit",
|
|
- "Virtual Mode Extensions",
|
|
- "Debugging Extensions",
|
|
- "Page Size Extensions",
|
|
- "Time Stamp Counter (with RDTSC and CR4 disable bit)",
|
|
- "Model Specific Registers with RDMSR & WRMSR",
|
|
- "PAE - Page Address Extensions",
|
|
- "Machine Check Exception",
|
|
- "COMPXCHG8B Instruction",
|
|
- "APIC",
|
|
- "10 - Reserved",
|
|
- "SYSCALL/SYSRET or SYSENTER/SYSEXIT instructions",
|
|
- "MTRR - Memory Type Range Registers",
|
|
- "Global paging extension",
|
|
- "Machine Check Architecture",
|
|
- "Conditional Move Instruction",
|
|
- "PAT - Page Attribute Table",
|
|
- "PSE-36 - Page Size Extensions",
|
|
- "18 - reserved",
|
|
- "19 - reserved",
|
|
- "20 - reserved",
|
|
- "21 - reserved",
|
|
- "AMD MMX Instruction Extensions",
|
|
- "MMX instructions",
|
|
- "FXSAVE/FXRSTOR",
|
|
- "25 - reserved",
|
|
- "26 - reserved",
|
|
- "27 - reserved",
|
|
- "28 - reserved",
|
|
- "29 - reserved",
|
|
- "3DNow! Instruction Extensions",
|
|
- "3DNow instructions",
|
|
+ "FPU Floating Point Unit",
|
|
+ "VME Virtual 8086 Mode Enhancements",
|
|
+ "DE Debugging Extensions",
|
|
+ "PSE Page Size Extensions",
|
|
+ "TSC Time Stamp Counter",
|
|
+ "MSR Model Specific Registers",
|
|
+ "PAE Physical Address Extension",
|
|
+ "MCE Machine Check Exception",
|
|
+ "CX8 COMPXCHG8B Instruction",
|
|
+ "APIC On-chip Advanced Programmable Interrupt Controller present and enabled",
|
|
+ "10 Reserved",
|
|
+ "SEP Fast System Call",
|
|
+ "MTRR Memory Type Range Registers",
|
|
+ "PGE PTE Global Flag",
|
|
+ "MCA Machine Check Architecture",
|
|
+ "CMOV Conditional Move and Compare Instructions",
|
|
+ "PAT Page Attribute Table",
|
|
+ "PSE36 36-bit Page Size Extension",
|
|
+ "18 Reserved",
|
|
+ "CLFSH CLFLUSH instruction",
|
|
+ "20 Reserved",
|
|
+ "21 Reserved",
|
|
+ "22 Reserved",
|
|
+ "MMX MMX instruction set",
|
|
+ "FXSR Fast FP/MMX Streaming SIMD Extensions save/restore",
|
|
+ "SSE SSE extensions",
|
|
+ "SSE2 SSE2 extensions",
|
|
+ "27 Reserved",
|
|
+ "HTT Hyper-Threading Technology",
|
|
+ "29 Reserved",
|
|
+ "30 Reserved",
|
|
+ "31 Reserved",
|
|
+};
|
|
+
|
|
+char *AMD_feature_flags2[] = {
|
|
+ "FPU Floating Point Unit",
|
|
+ "VME Virtual 8086 Mode Enhancements",
|
|
+ "DE Debugging Extensions",
|
|
+ "PSE Page Size Extensions",
|
|
+ "TSC Time Stamp Counter",
|
|
+ "MSR Model Specific Registers",
|
|
+ "PAE Physical Address Extension",
|
|
+ "MCE Machine Check Exception",
|
|
+ "CX8 COMPXCHG8B Instruction",
|
|
+ "APIC On-chip Advanced Programmable Interrupt Controller present and enabled",
|
|
+ "10 Reserved",
|
|
+ "SEP Fast System Call",
|
|
+ "MTRR Memory Type Range Registers",
|
|
+ "PGE PTE Global Flag",
|
|
+ "MCA Machine Check Architecture",
|
|
+ "CMOV Conditional Move and Compare Instructions",
|
|
+ "PAT Page Attribute Table",
|
|
+ "PSE36 36-bit Page Size Extension",
|
|
+ "18 Reserved",
|
|
+ "19 Reserved",
|
|
+ "NX No-execute page protection",
|
|
+ "21 Reserved",
|
|
+ "MmxExt MMX instruction extensions",
|
|
+ "MMX MMX instructions",
|
|
+ "FXSR Fast FP/MMX Streaming SIMD Extensions save/restore",
|
|
+ "FFXSR FXSAVE and FXRSTOR instruction optimizations",
|
|
+ "Pge1GB 1GB Page Support",
|
|
+ "RDTSCP RDTSCP instruction",
|
|
+ "28 Reserved",
|
|
+ "LM 64 bit long mode",
|
|
+ "3DNowE 3DNow! instruction extensions",
|
|
+ "3DNow 3DNow! instructions",
|
|
+};
|
|
+
|
|
+char *AMD_feature_flags3[] = {
|
|
+ "LhfSaf LAHF and SAHF instructions in 65-bit mode",
|
|
+ "CmpLeg Core Multi-Processing mode",
|
|
+ "SVM Secure Virtual Machine",
|
|
+ "XAPSPC Extended APIC Register Space",
|
|
+ "AltMC8 LOCK MOV CR0 means MOV CR8",
|
|
+ "ABM Advanced Bit Manipulation",
|
|
+ "SSE4A EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD support",
|
|
+ "MASSE Misaligned SSE mode",
|
|
+ "3DNPFC PREFETCH and PREFETCHW support",
|
|
+ "OSVW OS Visible Workaround support",
|
|
+ "10 Reserved",
|
|
+ "11 Reserved",
|
|
+ "SKINIT SKINIT, STGI, and DEV support",
|
|
+ "WDT Watchdog Timer support"
|
|
+ "14 Reserved",
|
|
+ "15 Reserved",
|
|
+ "16 Reserved",
|
|
+ "17 Reserved",
|
|
+ "18 Reserved",
|
|
+ "19 Reserved",
|
|
+ "20 Reserved",
|
|
+ "21 Reserved",
|
|
+ "22 Reserved",
|
|
+ "23 Reserved",
|
|
+ "24 Reserved",
|
|
+ "25 Reserved",
|
|
+ "26 Reserved",
|
|
+ "27 Reserved",
|
|
+ "28 Reserved",
|
|
+ "29 Reserved",
|
|
+ "30 Reserved",
|
|
+ "31 Reserved",
|
|
};
|
|
|
|
char *Assoc[] = {
|
|
@@ -657,10 +1042,16 @@
|
|
printf("Global Paging Extensions\n");
|
|
} else {
|
|
if(edx & (1<<i)){
|
|
- printf("%s\n",AMD_feature_flags[i]);
|
|
+ printf("%s\n",AMD_feature_flags2[i]);
|
|
}
|
|
}
|
|
}
|
|
+ printf("\nExtended Miscellaneous feature flags %08lx:\n", ecx);
|
|
+ for(i=0;i<32;i++){
|
|
+ if(ecx & (1<<i)){
|
|
+ printf("%s\n",AMD_feature_flags3[i]);
|
|
+ }
|
|
+ }
|
|
}
|
|
printf("\n");
|
|
if(maxei >= 0x80000002){
|