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c56fde6514
Fix worse runtime performance on Zen CPU when optimizing for Zen. [0] Install all standard heaaders with clang. Historically we've been unable to build FreeBSD with the full set due to conflicts and/or missing features between the compiler provided headers and FreeBSD's headers. I've verified that I can build world and kernel on the main, stable/14, and stable/13 branches for amd64 so let's give it another try in broader testing. [1] PR: 278908 [0], 274542 [1]
83 lines
4.3 KiB
Text
83 lines
4.3 KiB
Text
commit cadd2ca21765ebcb95b77ec94977b4e74e1edc1b
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Author: Dimitry Andric <dim@FreeBSD.org>
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Date: Sat May 25 19:52:15 2024 +0200
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Merge commit d0be944aa511 from llvm-project (by Simon Pilgrim):
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[X86] Add slow div64 tuning flag to Nehalem target (#91129)
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This appears to have been missed because later cpus don't inherit from Nehalem tuning much.
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Noticed while cleaning up for #90985
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Merge commit 8b400de79eff from llvm-project (by Simon Pilgrim):
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[X86] Enable TuningSlowDivide64 on Barcelona/Bobcat/Bulldozer/Ryzen Families (#91277)
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Despite most AMD cpus having a lower latency for i64 divisions that converge early, we are still better off testing for values representable as i32 and performing a i32 division if possible.
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All AMD cpus appear to have been missed when we added the "idivq-to-divl" attribute - this patch now matches Intel cpu behaviour (and the x86-64/v2/3/4 levels).
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Unfortunately the difference in code scheduling means I've had to stop using the update_llc_test_checks script and just use old-fashioned CHECK-DAG checks for divl/divq pairs.
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Fixes #90985
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This fixes possibly worse runtime performance on AMD Zen hardware, when
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using -march=znver4 (or any other znver), as opposed to -march=x86-64-v4
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or the baseline -march=x86-64. A similar fix is applied for Nehalem.
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PR: 278908
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MFC after: 3 days
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diff --git llvm/lib/Target/X86/X86.td llvm/lib/Target/X86/X86.td
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index e89ddcc570c9..1aff5f9fad97 100644
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--- llvm/lib/Target/X86/X86.td
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+++ llvm/lib/Target/X86/X86.td
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@@ -867,6 +867,7 @@ def ProcessorFeatures {
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// Nehalem
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list<SubtargetFeature> NHMFeatures = X86_64V2Features;
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list<SubtargetFeature> NHMTuning = [TuningMacroFusion,
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+ TuningSlowDivide64,
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TuningInsertVZEROUPPER,
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TuningNoDomainDelayMov];
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@@ -1336,6 +1337,7 @@ def ProcessorFeatures {
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FeatureCMOV,
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FeatureX86_64];
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list<SubtargetFeature> BarcelonaTuning = [TuningFastScalarShiftMasks,
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+ TuningSlowDivide64,
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TuningSlowSHLD,
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TuningSBBDepBreaking,
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TuningInsertVZEROUPPER];
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@@ -1358,6 +1360,7 @@ def ProcessorFeatures {
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list<SubtargetFeature> BtVer1Tuning = [TuningFast15ByteNOP,
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TuningFastScalarShiftMasks,
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TuningFastVectorShiftMasks,
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+ TuningSlowDivide64,
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TuningSlowSHLD,
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TuningSBBDepBreaking,
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TuningInsertVZEROUPPER];
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@@ -1380,6 +1383,7 @@ def ProcessorFeatures {
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TuningFastVectorShiftMasks,
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TuningFastMOVBE,
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TuningSBBDepBreaking,
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+ TuningSlowDivide64,
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TuningSlowSHLD];
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list<SubtargetFeature> BtVer2Features =
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!listconcat(BtVer1Features, BtVer2AdditionalFeatures);
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@@ -1404,6 +1408,7 @@ def ProcessorFeatures {
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FeatureLWP,
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FeatureLAHFSAHF64];
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list<SubtargetFeature> BdVer1Tuning = [TuningSlowSHLD,
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+ TuningSlowDivide64,
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TuningFast11ByteNOP,
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TuningFastScalarShiftMasks,
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TuningBranchFusion,
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@@ -1483,6 +1488,7 @@ def ProcessorFeatures {
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TuningFastScalarShiftMasks,
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TuningFastVariablePerLaneShuffle,
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TuningFastMOVBE,
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+ TuningSlowDivide64,
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TuningSlowSHLD,
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TuningSBBDepBreaking,
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TuningInsertVZEROUPPER,
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