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21bae5bc77
Add patches for head rS342592 and rS342593 (D18691) Add patch files for head rS342592 and rS342593, which correspond to the following upstream revisions: https://reviews.llvm.org/rL342397 https://reviews.llvm.org/rL342397 These fix an 'Assertion failed: ((VT.getVectorNumElements() + N2C->getZExtValue() <= N1.getValueType().getVectorNumElements()) && "Extract subvector overflow!"), function getNode' when building the multimedia/aom port (with AVX2 enabled). PR: 234480 Submitted by: theraven, dim Differential Revision: https://reviews.freebsd.org/D18672 Differential Revision: https://reviews.freebsd.org/D18691
106 lines
5.2 KiB
Diff
106 lines
5.2 KiB
Diff
r342592 | dim | 2018-12-29 16:13:49 +0100 (Sat, 29 Dec 2018) | 19 lines
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Pull in r342397 from upstream llvm trunk (by Amara Emerson):
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Revert "Revert r342183 "[DAGCombine] Fix crash when store merging
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created an extract_subvector with invalid index.""
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Fixed the assertion failure.
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Differential Revision: https://reviews.llvm.org/D51831
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This fixes 'Assertion failed: ((VT.getVectorNumElements() +
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N2C->getZExtValue() <= N1.getValueType().getVectorNumElements()) &&
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"Extract subvector overflow!"), function getNode' when building the
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multimedia/aom port (with AVX2 enabled).
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Reported by: jbeich
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PR: 234480
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Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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===================================================================
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--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp (revision 342591)
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+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp (revision 342592)
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@@ -13727,10 +13727,19 @@ bool DAGCombiner::MergeStoresOfConstantsOrVecElts(
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Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) {
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SDValue Vec = Val.getOperand(0);
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EVT MemVTScalarTy = MemVT.getScalarType();
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+ SDValue Idx = Val.getOperand(1);
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// We may need to add a bitcast here to get types to line up.
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if (MemVTScalarTy != Vec.getValueType()) {
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unsigned Elts = Vec.getValueType().getSizeInBits() /
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MemVTScalarTy.getSizeInBits();
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+ if (Val.getValueType().isVector() && MemVT.isVector()) {
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+ unsigned IdxC = cast<ConstantSDNode>(Idx)->getZExtValue();
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+ unsigned NewIdx =
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+ ((uint64_t)IdxC * MemVT.getVectorNumElements()) / Elts;
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+ Idx = DAG.getConstant(NewIdx, SDLoc(Val), Idx.getValueType());
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+ }
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+ if (!MemVT.isVector() && Val.getValueType().isVector())
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+ dbgs() << "hit!\n";
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EVT NewVecTy =
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EVT::getVectorVT(*DAG.getContext(), MemVTScalarTy, Elts);
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Vec = DAG.getBitcast(NewVecTy, Vec);
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@@ -13737,7 +13746,7 @@ bool DAGCombiner::MergeStoresOfConstantsOrVecElts(
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}
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auto OpC = (MemVT.isVector()) ? ISD::EXTRACT_SUBVECTOR
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: ISD::EXTRACT_VECTOR_ELT;
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- Val = DAG.getNode(OpC, SDLoc(Val), MemVT, Vec, Val.getOperand(1));
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+ Val = DAG.getNode(OpC, SDLoc(Val), MemVT, Vec, Idx);
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}
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Ops.push_back(Val);
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}
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Index: test/CodeGen/X86/merge-vector-stores-scale-idx-crash.ll
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===================================================================
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--- test/CodeGen/X86/merge-vector-stores-scale-idx-crash.ll (nonexistent)
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+++ test/CodeGen/X86/merge-vector-stores-scale-idx-crash.ll (revision 342592)
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@@ -0,0 +1,49 @@
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+; RUN: llc < %s -mtriple=x86_64-apple-osx10.14 -mattr=+avx2 | FileCheck %s
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+
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+; Check that we don't crash due creating invalid extract_subvector indices in store merging.
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+; CHECK-LABEL: testfn
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+; CHECK: retq
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+define void @testfn(i32* nocapture %p) {
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+ %v0 = getelementptr i32, i32* %p, i64 12
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+ %1 = bitcast i32* %v0 to <2 x i64>*
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+ %2 = bitcast i32* %v0 to <4 x i32>*
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+ %3 = getelementptr <2 x i64>, <2 x i64>* %1, i64 -3
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+ store <2 x i64> undef, <2 x i64>* %3, align 16
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+ %4 = shufflevector <4 x i64> zeroinitializer, <4 x i64> undef, <2 x i32> <i32 0, i32 1>
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+ %5 = getelementptr <2 x i64>, <2 x i64>* %1, i64 -2
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+ store <2 x i64> %4, <2 x i64>* %5, align 16
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+ %6 = shufflevector <8 x i32> zeroinitializer, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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+ %7 = getelementptr <4 x i32>, <4 x i32>* %2, i64 -1
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+ store <4 x i32> %6, <4 x i32>* %7, align 16
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+ ret void
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+}
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+
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+%struct.o.1.5.7.9.13.15.17.19.57 = type { [0 x %struct.d.0.4.6.8.12.14.16.18.56] }
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+%struct.d.0.4.6.8.12.14.16.18.56 = type { float, float }
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+
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+; CHECK-LABEL: testfn_scalar
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+; CHECK: retq
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+define void @testfn_scalar(%struct.o.1.5.7.9.13.15.17.19.57* nocapture %j) local_unnamed_addr #0 align 2 {
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+entry:
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+ %0 = bitcast i64 undef to <2 x float>
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+ br i1 undef, label %if.end, label %if.then
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+
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+if.then: ; preds = %entry
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+ unreachable
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+
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+if.end: ; preds = %entry
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+ %call.i.i17 = tail call <4 x float> @_Z1bv()
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+ %1 = bitcast <4 x float> %call.i.i17 to <2 x i64>
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+ %extract.i.i15 = extractelement <2 x i64> %1, i64 0
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+ %arrayidx6 = getelementptr inbounds %struct.o.1.5.7.9.13.15.17.19.57, %struct.o.1.5.7.9.13.15.17.19.57* %j, i64 0, i32 0, i64 1
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+ %2 = bitcast %struct.d.0.4.6.8.12.14.16.18.56* %arrayidx6 to i64*
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+ store i64 %extract.i.i15, i64* %2, align 4
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+ %r.sroa.0.0..sroa_cast12 = bitcast %struct.o.1.5.7.9.13.15.17.19.57* %j to <2 x float>*
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+ store <2 x float> %0, <2 x float>* %r.sroa.0.0..sroa_cast12, align 4
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+ ret void
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+}
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+
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+declare <4 x float> @_Z1bv() local_unnamed_addr
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+
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+attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
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+
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