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This adds all the patches that were applied in the past to head, under contrib/llvm. After these, there only minimal diffs left between the port sources and the base sources. Most of these remaining diffs are due to #ifdef shortcuts in the base sources, because we don't compile certain features in. Other diffs are because the port has applied a few changes that we don't have in base. While here, use Makefile.LICENSE from the devel/llvm-devel port. Approved by: brooks (maintainer) Reviewed by: brooks PR: 212343, 225128, 225471, 226388, 226658, 226872, 229050, 230444, 230604, 231355 MFH: 2018Q4 Differential Revision: https://reviews.freebsd.org/D17702
80 lines
2.8 KiB
Diff
80 lines
2.8 KiB
Diff
r330686 | dim | 2018-03-09 10:21:22 +0100 (Fri, 09 Mar 2018) | 20 lines
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Pull in r326882 from upstream llvm trunk (by Sjoerd Meijer):
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[ARM] Fix for PR36577
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Don't PerformSHLSimplify if the given node is used by a node that
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also uses a constant because we may get stuck in an infinite combine
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loop.
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bugzilla: https://bugs.llvm.org/show_bug.cgi?id=36577
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Patch by Sam Parker.
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Differential Revision: https://reviews.llvm.org/D44097
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This fixes a hang when compiling one particular file in java/openjdk8
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for armv6 and armv7.
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Reported by: swills
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PR: 226388
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Index: lib/Target/ARM/ARMISelLowering.cpp
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===================================================================
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--- lib/Target/ARM/ARMISelLowering.cpp (revision 330685)
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+++ lib/Target/ARM/ARMISelLowering.cpp (revision 330686)
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@@ -10201,7 +10201,14 @@ static SDValue PerformSHLSimplify(SDNode *N,
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case ISD::XOR:
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case ISD::SETCC:
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case ARMISD::CMP:
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- // Check that its not already using a shl.
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+ // Check that the user isn't already using a constant because there
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+ // aren't any instructions that support an immediate operand and a
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+ // shifted operand.
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+ if (isa<ConstantSDNode>(U->getOperand(0)) ||
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+ isa<ConstantSDNode>(U->getOperand(1)))
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+ return SDValue();
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+
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+ // Check that it's not already using a shift.
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if (U->getOperand(0).getOpcode() == ISD::SHL ||
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U->getOperand(1).getOpcode() == ISD::SHL)
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return SDValue();
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@@ -10223,8 +10230,6 @@ static SDValue PerformSHLSimplify(SDNode *N,
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if (!C1ShlC2 || !C2)
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return SDValue();
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- DEBUG(dbgs() << "Trying to simplify shl: "; N->dump());
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-
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APInt C2Int = C2->getAPIntValue();
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APInt C1Int = C1ShlC2->getAPIntValue();
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@@ -10238,12 +10243,12 @@ static SDValue PerformSHLSimplify(SDNode *N,
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C1Int.lshrInPlace(C2Int);
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// The immediates are encoded as an 8-bit value that can be rotated.
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- unsigned Zeros = C1Int.countLeadingZeros() + C1Int.countTrailingZeros();
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- if (C1Int.getBitWidth() - Zeros > 8)
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- return SDValue();
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+ auto LargeImm = [](const APInt &Imm) {
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+ unsigned Zeros = Imm.countLeadingZeros() + Imm.countTrailingZeros();
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+ return Imm.getBitWidth() - Zeros > 8;
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+ };
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- Zeros = C2Int.countLeadingZeros() + C2Int.countTrailingZeros();
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- if (C2Int.getBitWidth() - Zeros > 8)
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+ if (LargeImm(C1Int) || LargeImm(C2Int))
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return SDValue();
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SelectionDAG &DAG = DCI.DAG;
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@@ -10254,6 +10259,10 @@ static SDValue PerformSHLSimplify(SDNode *N,
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// Shift left to compensate for the lshr of C1Int.
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SDValue Res = DAG.getNode(ISD::SHL, dl, MVT::i32, BinOp, SHL.getOperand(1));
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+ DEBUG(dbgs() << "Simplify shl use:\n"; SHL.getOperand(0).dump(); SHL.dump();
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+ N->dump());
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+ DEBUG(dbgs() << "Into:\n"; X.dump(); BinOp.dump(); Res.dump());
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+
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DAG.ReplaceAllUsesWith(SDValue(N, 0), Res);
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return SDValue(N, 0);
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}
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