sync/ports
1
0
Fork 0
mirror of https://git.freebsd.org/ports.git synced 2025-06-15 17:50:31 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions
576117 commits 47 branches 104 tags 1.8 GiB
Commit graph

39 commits

Author SHA1 Message Date
Yuri Victorovich
375838933d cad/verilator: Update 4.216 -> 4.218 2022-01-24 21:44:21 -08:00
Yuri Victorovich
1eae61419a cad/verilator: Update 4.214 -> 4.216 
Reported by:	portscout
 2021-12-12 13:52:38 -08:00
Yuri Victorovich
f8d93a673b cad/verilator: Update 4.212 -> 4.214 
Reported by:	portscout
 2021-10-20 17:46:01 -07:00
Yuri Victorovich
6d28c13f73 cad/verilator: Use GNU ar from devel/binutils 
verilator requires the GNU ar feature: '@' file prefix indicating
that the file contains command-line options.

Reference: https://github.com/verilator/verilator/issues/2999

Reported by:	Antonin Houska <ah@melesmeles.cz>
 2021-09-30 09:10:42 -07:00
Yuri Victorovich
12d08248c8 cad/verilator: Cosmetic fix - use bash as configure shell 2021-09-13 15:46:09 -07:00
Yuri Victorovich
6453e58124 cad/verilator: Update 4.210 -> 4.212 
Project doesn't distribute tarballs any more in favor of GitHub
tags.
 2021-09-13 15:29:00 -07:00
Yuri Victorovich
f41cab0fad cad/verilator: Backport the fix of bug that caused wrong C++ code generation 2021-08-25 13:28:24 -07:00
Yuri Victorovich
b26747b307 cad/verilator: Update 4.204 -> 4.210 2021-08-03 01:36:58 -07:00
Yuri Victorovich
296d661f61 cad/verilator: Broken on i386 
Reported by:	fallout
 2021-06-22 01:54:47 -07:00
Yuri Victorovich
a6079c8520 cad/verilator: Update 4.202 -> 4.204 2021-06-18 10:16:57 -07:00
Yuri Victorovich
dfb9884fac cad/verilator: Backport of fix of missing #include <array> bug. 2021-06-07 13:41:13 -07:00
Yuri Victorovich
808dd5abe3 cad/verilator: Update 4.200 -> 4.202 2021-04-24 15:18:59 -07:00
Mathieu Arnold
cf118ccf87
One more small cleanup, forgotten yesterday. 
Reported by:	lwhsu
 2021-04-07 10:09:01 +02:00
Mathieu Arnold
305f148f48
Remove # $FreeBSD$ from Makefiles. 2021-04-06 16:31:07 +02:00
Yuri Victorovich
0955b90dfe cad/verilator: Update 4.110 -> 4.200 2021-03-20 01:29:51 +00:00
Yuri Victorovich
b53aaf78ce cad/verilator: Update 4.108 -> 4.110 2021-02-27 04:19:01 +00:00
Sunpoet Po-Chuan Hsieh
becaac537e Fix build with bison 3.7.4 
PR:		248911
Exp-run by:	antoine
 2021-01-26 13:59:25 +00:00
Yuri Victorovich
419ef9470f cad/verilator: Update 4.106 -> 4.108 2021-01-13 02:00:39 +00:00
Yuri Victorovich
c67e88ab7b cad/verilator: Update 4.104 -> 4.106 2020-12-06 20:23:03 +00:00
Yuri Victorovich
e0ff11d8bc cad/verilator: Update 4.102 -> 4.104 2020-11-17 19:35:08 +00:00
Yuri Victorovich
874edc67e1 cad/verilator: Update 4.100 -> 4.102 2020-10-15 22:11:24 +00:00
Yuri Victorovich
682057a1e3 cad/verilator: Add the run-tim dependency on gmake 2020-09-16 04:29:35 +00:00
Yuri Victorovich
a9637bca50 cad/verilator: Update 4.040 -> 4.100 2020-09-15 06:05:46 +00:00
Yuri Victorovich
695b5d9945 cad/verilator: Add options INSTALL_DBG_EXECUTABLES and LEAK_CHECKS 2020-09-11 20:13:57 +00:00
Yuri Victorovich
a28dea55f5 cad/verilator: Add the SystemC dependency 
Also:
* Remove unnecessary patch that has been already applied upstream
* Fix BINARY_ALIAS added for testing
 2020-09-01 03:14:17 +00:00
Yuri Victorovich
607d352096 cad/verilator: Add the 'test' target 2020-09-01 01:57:59 +00:00
Yuri Victorovich
a9f7cc5505 cad/verilator: Update 4.038 -> 4.040 
Taking maintainership based on the maintainer's request.

PR:		248713
Approved by:	kevinz5000@gmail.com (maintainer)
 2020-08-18 17:56:39 +00:00
Yuri Victorovich
9eb83d06fe cad/verilator: Update 4.036 -> 4.038 
PR:		248086
Approved by:	kevinz5000@gmail.com (maintainer)
 2020-07-18 23:00:44 +00:00
Yuri Victorovich
14ffdbe6f1 cad/verilator: Update 4.034 -> 4.036 
PR:		247858
Approved by:	kevinz5000@gmail.com (maintainer)
 2020-07-08 22:53:00 +00:00
Sunpoet Po-Chuan Hsieh
3f66b8f906 Fix build with bison 3.6.2 2020-05-25 18:25:19 +00:00
Yuri Victorovich
84b0509b58 cad/verilator: Update 4.028 -> 4.034 
PR:		243698
Approved by:	kevinz5000@gmail.com (maintainer's timeout; 110 days)
 2020-05-23 19:04:30 +00:00
Yuri Victorovich
0f2b912e40 cad/verilator: Update 4.024 -> 4.028 
PR:		244067
Approved by:	kevinz5000@gmail.com (maintainer)
 2020-02-12 07:31:51 +00:00
Yuri Victorovich
9f2cefb4ee cad/verilator: Update 4.020 -> 4.024 
PR:		243107
Approved by:	kevinz5000@gmail.com (maintainer)
 2020-01-05 08:00:43 +00:00
Yuri Victorovich
6ead058b02 cad/verilator: Update 4.008 -> 4.020 
PR:		241346
Approved by:	kevinz5000@gmail.com (maintainer)
 2019-10-19 22:07:56 +00:00
Gerald Pfeifer
ea8c8ec7da Bump PORTREVISION for ports depending on the canonical version of GCC 
as defined in Mk/bsd.default-versions.mk which has moved from GCC 8.3
to GCC 9.1 under most circumstances now after revision 507371.

This includes ports
 - with USE_GCC=yes or USE_GCC=any,
 - with USES=fortran,
 - using Mk/bsd.octave.mk which in turn features USES=fortran, and
 - with USES=compiler specifying openmp, nestedfct, c11, c++0x, c++11-lang,
   c++11-lib, c++14-lang, c++17-lang, or gcc-c++11-lib
plus, everything INDEX-11 shows with a dependency on lang/gcc9 now.

PR:		238330
 2019-07-26 20:46:53 +00:00
Mark Linimon
0d3b4868e7 Fix build on gcc-based architectures: 
configure: error: the c++ compiler appears to not support C++11.

Approved by:	portmgr (tier-2 blanket)
 2019-03-13 05:24:21 +00:00
Steve Wills
250d86f4fc cad/verilator: remove unnecessary BUILD_DEPENDS 
PR:		235053
Submitted by:	John Hein <jcfyecrayz@liamekaens.com>
Approved by:	Kevin Zheng <kevinz5000@gmail.com> (maintainer)
 2019-01-27 12:34:34 +00:00
Steve Wills
1418f410db cad/verilator: update to 4.008 
PR:		235228
Approved by:	kevinz5000@gmail.com (maintainer)
 2019-01-27 12:25:31 +00:00
Steve Wills
5eee19a826 cad/verilator: create port 
Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.

WWW: https://www.veripool.org/projects/verilator/wiki/Intro

PR:		230761
Submitted by:	Kevin Zheng <kevinz5000@gmail.com>
 2019-01-17 23:27:11 +00:00