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cad/qflow: update 1.4.103 → 1.4.104

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PR:	282679
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Älven 2024-11-10 15:52:38 -08:00 • committed by Yuri Victorovich
parent a0a30f20be
commit e192a5b6b3
3 changed files with 5 additions and 5 deletions
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2
cad/qflow/Makefile
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@ -1,5 +1,5 @@
PORTNAME= qflow
DISTVERSION= 1.4.103
DISTVERSION= 1.4.104
CATEGORIES= cad
MAINTAINER= yuri@FreeBSD.org

6
cad/qflow/distinfo
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@ -1,3 +1,3 @@
TIMESTAMP = 1714976162
SHA256 (RTimothyEdwards-qflow-1.4.103_GH0.tar.gz) = 8d04b14c94ae57e41efa4cdaa014150f57cd2f4fdccd48fb8bc50bac3ce06bea
SIZE (RTimothyEdwards-qflow-1.4.103_GH0.tar.gz) = 946044
TIMESTAMP = 1731246856
SHA256 (RTimothyEdwards-qflow-1.4.104_GH0.tar.gz) = 48297322780cc2552a49f662b245809e8cb5fb286aac4b43734c36ff75f83c21
SIZE (RTimothyEdwards-qflow-1.4.104_GH0.tar.gz) = 946203

2
cad/qflow/pkg-descr
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@ -1,5 +1,5 @@
A digital synthesis flow is a set of tools and methods used to turn a circuit
design written in a high-level behavioral language like verilog or VHDL into a
design written in a high-level behavioral language like Verilog or VHDL into a
physical circuit, which can either be configuration code for an FPGA target like
a Xilinx or Altera chip, or a layout in a specific fabrication process
technology, that would become part of a fabricated circuit chip. Several digital