sync/ports
1
0
Fork 0
mirror of https://git.freebsd.org/ports.git synced 2025-07-18 17:59:20 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Point to the new home

Browse source 
Make it fetchable again
This commit is contained in:
Baptiste Daroussin 2011-06-16 10:41:31 +00:00
parent 2bff51c762
commit d4ad06791f
Notes: svn2git 2021-03-31 03:12:20 +00:00 
svn path=/head/; revision=275669
2 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
cad/gplcver/Makefile
View file

@ -9,7 +9,7 @@
PORTNAME= gplcver
PORTVERSION= 2.12.a
CATEGORIES= cad
MASTER_SITES= http://www.pragmatic-c.com/gpl-cver/downloads/
MASTER_SITES= SF/${PORTNAME}/${PORTNAME}/${PORTVERSION:R}${PORTVERSION:E}/
DISTNAME= ${PORTNAME}-${PORTVERSION:R}${PORTVERSION:E}.src
MAINTAINER= ports@FreeBSD.org

2
cad/gplcver/pkg-descr
View file

@ -15,4 +15,4 @@ Manual (LRM) that can be purchased from IEEE. There are many good books
for learning that teach the Verilog HDL and/or that teach digital circuit
design using Verilog.
WWW: http://www.pragmatic-c.com/gpl-cver/
WWW: http://sourceforge.net/projects/gplcver/