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cad/yosys: update 0.41 → 0.42

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Reported by:	portscout
This commit is contained in:
Yuri Victorovich 2024-06-08 01:04:11 -07:00
parent 354276d399
commit ca43cdbcc4
3 changed files with 5 additions and 8 deletions
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2
cad/yosys/Makefile
View file

@ -1,6 +1,6 @@
PORTNAME= yosys
DISTVERSIONPREFIX= yosys-
DISTVERSION= 0.41
DISTVERSION= 0.42
CATEGORIES= cad
MAINTAINER= yuri@FreeBSD.org

6
cad/yosys/distinfo
View file

@ -1,3 +1,3 @@
TIMESTAMP = 1716572266
SHA256 (YosysHQ-yosys-yosys-0.41_GH0.tar.gz) = b0037d0a5864550a07a72ba81346e52a7d5f76b3027ef1d7c71b975d2c8bd2b2
SIZE (YosysHQ-yosys-yosys-0.41_GH0.tar.gz) = 2808657
TIMESTAMP = 1717824447
SHA256 (YosysHQ-yosys-yosys-0.42_GH0.tar.gz) = 359714de8378665edebfacdf996b5f4f2fa55bf33071fc92ad6e08b5c4bdb648
SIZE (YosysHQ-yosys-yosys-0.42_GH0.tar.gz) = 2807211

5
cad/yosys/pkg-plist
View file

@ -101,9 +101,9 @@ bin/yosys-witness
%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc
%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h
%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h
%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h
%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h
%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h
%%DATADIR%%/include/backends/rtlil/rtlil_backend.h
%%DATADIR%%/include/frontends/ast/ast.h
%%DATADIR%%/include/frontends/ast/ast_binding.h
@ -164,8 +164,6 @@ bin/yosys-witness
%%DATADIR%%/intel_alm/common/arith_alm_map.v
%%DATADIR%%/intel_alm/common/bram_m10k.txt
%%DATADIR%%/intel_alm/common/bram_m10k_map.v
%%DATADIR%%/intel_alm/common/bram_m20k.txt
%%DATADIR%%/intel_alm/common/bram_m20k_map.v
%%DATADIR%%/intel_alm/common/dff_map.v
%%DATADIR%%/intel_alm/common/dff_sim.v
%%DATADIR%%/intel_alm/common/dsp_map.v
@ -174,7 +172,6 @@ bin/yosys-witness
%%DATADIR%%/intel_alm/common/megafunction_bb.v
%%DATADIR%%/intel_alm/common/mem_sim.v
%%DATADIR%%/intel_alm/common/misc_sim.v
%%DATADIR%%/intel_alm/common/quartus_rename.v
%%DATADIR%%/intel_alm/cyclonev/cells_sim.v
%%DATADIR%%/lattice/arith_map_ccu2c.v
%%DATADIR%%/lattice/arith_map_ccu2d.v