diff --git a/cad/verilator/Makefile b/cad/verilator/Makefile
index 4f94768e3255..cae1b5fc3457 100644
--- a/cad/verilator/Makefile
+++ b/cad/verilator/Makefile
@@ -1,14 +1,14 @@
 # $FreeBSD$
 
 PORTNAME=	verilator
-DISTVERSION=	4.038
+DISTVERSION=	4.040
 CATEGORIES=	cad
 MASTER_SITES=	https://www.veripool.org/ftp/
 
 PATCH_SITES=	https://github.com/${PORTNAME}/${PORTNAME}/commit/
 PATCHFILES+=	39f16fb155b9e909f919a9d4ae06890395987b16.patch:-p1 # https://github.com/verilator/verilator/pull/2353
 
-MAINTAINER=	kevinz5000@gmail.com
+MAINTAINER=	yuri@FreeBSD.org
 COMMENT=	Synthesizable Verilog to C++ compiler
 
 LICENSE=	GPLv3
diff --git a/cad/verilator/distinfo b/cad/verilator/distinfo
index 3f03c315e6c4..2c4667b6be7c 100644
--- a/cad/verilator/distinfo
+++ b/cad/verilator/distinfo
@@ -1,5 +1,5 @@
-TIMESTAMP = 1595108832
-SHA256 (verilator-4.038.tgz) = fa004493216034ac3e26b21b814441bd5801592f4f269c5a4672e3351d73b515
-SIZE (verilator-4.038.tgz) = 2703465
+TIMESTAMP = 1597706592
+SHA256 (verilator-4.040.tgz) = 6e1574924083922a4eb80ff22eedc866f4ce54e5fd6a34101b6af7aa29e5c0e3
+SIZE (verilator-4.040.tgz) = 2720606
 SHA256 (39f16fb155b9e909f919a9d4ae06890395987b16.patch) = 266c63d54bc00d4a67163b701a10cf238faf9c21f04e0c8192bd5495ff000b80
 SIZE (39f16fb155b9e909f919a9d4ae06890395987b16.patch) = 590