sync/ports
1
0
Fork 0
mirror of https://git.freebsd.org/ports.git synced 2025-06-01 19:06:28 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

cad/iverilog: Update 11.0 → 12_0

Browse source 
PR:	270908
Approved by:	kbowling@
This commit is contained in:
Yuri Victorovich 2023-04-18 08:54:24 -07:00
parent c504528538
commit 8d90ef126d
2 changed files with 16 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
cad/iverilog/Makefile
View file

@ -1,18 +1,26 @@
PORTNAME= iverilog
PORTVERSION= 11.0
DISTVERSIONPREFIX= v
DISTVERSION= 12_0
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v11/
DISTNAME= verilog-${PORTVERSION}
MAINTAINER= kbowling@FreeBSD.org
COMMENT= Verilog simulation and synthesis tool
WWW= http://iverilog.icarus.com/
WWW= https://steveicarus.github.io/iverilog/
LICENSE= GPLv2
BUILD_DEPENDS= autoconf:devel/autoconf \
gperf:devel/gperf
USES= bison compiler:c++11-lang gmake readline
USE_GITHUB= yes
GH_ACCOUNT= steveicarus
GNU_CONFIGURE= yes
CONFIGURE_ARGS= --disable-suffix
USES= bison compiler:c++11-lang gmake readline
pre-configure:
@cd ${WRKSRC} && sh autoconf.sh
.include <bsd.port.mk>

6
cad/iverilog/distinfo
View file

@ -1,3 +1,3 @@
TIMESTAMP = 1603302018
SHA256 (verilog-11.0.tar.gz) = d54785616b63fe6739948e9967499624f29ded54adb57e1e00eb897567a655d5
SIZE (verilog-11.0.tar.gz) = 1784307
TIMESTAMP = 1681749176
SHA256 (steveicarus-iverilog-v12_0_GH0.tar.gz) = a68cb1ef7c017ef090ebedb2bc3e39ef90ecc70a3400afb4aa94303bc3beaa7d
SIZE (steveicarus-iverilog-v12_0_GH0.tar.gz) = 2995096