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New port: devel/lattice-ice40-tools

Browse source 
Metaport which enables a fully open source Verilog-to-Bitstream
flow for iCE40 FPGAs.

WWW: http://www.clifford.at/icestorm

PR:		227592
Submitted by:	Johnny Sorocil <jsorocil@gmail.com>
Differential Revision:	https://reviews.freebsd.org/D15632
This commit is contained in:
Tobias Kortkamp 2018-06-06 14:52:57 +00:00
parent 9fe92012ef
commit 31c85bb7cf
Notes: svn2git 2021-03-31 03:12:20 +00:00 
svn path=/head/; revision=471848
4 changed files with 35 additions and 0 deletions
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1
devel/Makefile
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@ -1329,6 +1329,7 @@
SUBDIR += lasi
SUBDIR += lattice-ice40-examples-hx1k
SUBDIR += lattice-ice40-examples-hx8k
SUBDIR += lattice-ice40-tools
SUBDIR += lcov
SUBDIR += leaktracer
SUBDIR += leatherman

25
devel/lattice-ice40-tools/Makefile Normal file
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@ -0,0 +1,25 @@
# Created by: Johnny Sorocil <jsorocil@gmail.com>
# $FreeBSD$
PORTNAME= lattice-ice40-tools
PORTVERSION= g20180310
CATEGORIES= devel
MAINTAINER= jsorocil@gmail.com
COMMENT= Open source tools for Lattice iCE40 FPGAs
RUN_DEPENDS= abc:cad/abc \
arachne-pnr:devel/arachne-pnr \
icepack:devel/icestorm \
yosys:devel/yosys
USES= metaport
OPTIONS_DEFINE= EXAMPLES
EXAMPLES_DESC= Build examples for Olimex iCE40 FPGA boards
EXAMPLES_RUN_DEPENDS= lattice-ice40-examples-hx1k>=g0:devel/lattice-ice40-examples-hx1k \
lattice-ice40-examples-hx8k>=g0:devel/lattice-ice40-examples-hx8k
.include <bsd.port.mk>

5
devel/lattice-ice40-tools/distinfo Normal file
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@ -0,0 +1,5 @@
TIMESTAMP = 1528041379
SHA256 (OLIMEX-iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492_GH0.tar.gz) = 99a6328ccfcd7a6a8a25d1521c028d1a1b5418b7de1dcc3b2db40e7d1bed9034
SIZE (OLIMEX-iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492_GH0.tar.gz) = 2181827
SHA256 (OLIMEX-iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612_GH0.tar.gz) = 1f6d29d1420f608fda49f1b50085453bd4c6d32067773d210af386f95b24bd3a
SIZE (OLIMEX-iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612_GH0.tar.gz) = 1370726

4
devel/lattice-ice40-tools/pkg-descr Normal file
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@ -0,0 +1,4 @@
Metaport which enables a fully open source Verilog-to-Bitstream
flow for iCE40 FPGAs.
WWW: http://www.clifford.at/icestorm