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cad/verilator: update 5.026 → 5.028

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Reported by:	portscout
This commit is contained in:
Yuri Victorovich 2024-08-25 11:16:43 -07:00
parent 3ecf245bfa
commit 0d19462826
3 changed files with 4 additions and 14 deletions
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2
cad/verilator/Makefile
View file

@ -1,6 +1,6 @@
PORTNAME= verilator
DISTVERSIONPREFIX= v
DISTVERSION= 5.026
DISTVERSION= 5.028
CATEGORIES= cad
MAINTAINER= yuri@FreeBSD.org

6
cad/verilator/distinfo
View file

@ -1,3 +1,3 @@
TIMESTAMP = 1718513016
SHA256 (verilator-verilator-v5.026_GH0.tar.gz) = 87fdecf3967007d9ee8c30191ff2476f2a33635d0e0c6e3dbf345cc2f0c50b78
SIZE (verilator-verilator-v5.026_GH0.tar.gz) = 3931397
TIMESTAMP = 1724606521
SHA256 (verilator-verilator-v5.028_GH0.tar.gz) = 02d4b6f34754b46a97cfd70f5fcbc9b730bd1f0a24c3fc37223397778fcb142c
SIZE (verilator-verilator-v5.028_GH0.tar.gz) = 32547892

10
cad/verilator/files/patch-src-verilog.y
View file

@ -1,10 +0,0 @@
--- src/verilog.y.orig 2020-08-14 11:38:09 UTC
+++ src/verilog.y
@@ -31,7 +31,6 @@
#include <cstdarg>
#include <stack>
-#define YYERROR_VERBOSE 1 // For prior to Bison 3.6
#define YYINITDEPTH 10000 // Older bisons ignore YYMAXDEPTH
#define YYMAXDEPTH 10000