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Maintainer Update to latest snapshot. Changes: add AMD64 support

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(experimental); time 0 race resolution; identation cleanup; manpage
update.
PR: ports/58320
This commit is contained in:
Mark Linimon 2003-10-27 10:02:34 +00:00
parent a8472f5981
commit 09752ef262
Notes: svn2git 2021-03-31 03:12:20 +00:00 
svn path=/head/; revision=92314
3 changed files with 4 additions and 5 deletions
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6
cad/iverilog/Makefile
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@ -7,12 +7,10 @@
# #
PORTNAME= iverilog PORTNAME= iverilog
PORTVERSION= 0.7.20030722 PORTVERSION= 0.7.20031009
CATEGORIES= cad CATEGORIES= cad
#MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION}/
#DISTNAME= verilog-${PORTVERSION}
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/ MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
DISTNAME= verilog-20030722 DISTNAME= verilog-20031009
MAINTAINER= watchman@ludd.luth.se MAINTAINER= watchman@ludd.luth.se
COMMENT= A Verilog simulation and synthesis tool COMMENT= A Verilog simulation and synthesis tool

2
cad/iverilog/distinfo
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@ -1 +1 @@
MD5 (verilog-20030722.tar.gz) = b435baa100fb368a9cfc12f510af9c6e MD5 (verilog-20031009.tar.gz) = d4d78212b4f7dde22555cdac5a52b468

1
cad/iverilog/pkg-plist
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@ -5,6 +5,7 @@ include/acc_user.h
include/ivl_target.h include/ivl_target.h
include/veriuser.h include/veriuser.h
include/vpi_user.h include/vpi_user.h
lib/ivl/cadpli.vpl
lib/ivl/fpga.tgt lib/ivl/fpga.tgt
lib/ivl/iverilog.conf lib/ivl/iverilog.conf
lib/ivl/ivl lib/ivl/ivl