- Update to version 0.9.5

- Add LICENSE
- Update project homepage

PR:		ports/162280
Submitted by:	Niclas Zeising <niclas.zeising@gmail.com> (maintainer)

cad/iverilog/Makefile

@@ -7,7 +7,7 @@
 #
 
 PORTNAME=	iverilog
-PORTVERSION=	0.9.4
+PORTVERSION=	0.9.5
 CATEGORIES=	cad
 MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]$,,}/ \
 		ftp://ftp.geda.seul.org/pub/geda/dist/
@@ -16,6 +16,8 @@ DISTNAME=	verilog-${PORTVERSION}
 MAINTAINER=	niclas.zeising@gmail.com
 COMMENT=	A Verilog simulation and synthesis tool
 
+LICENSE=	GPLv2
+
 GNU_CONFIGURE=	yes
 USE_BISON=	build
 USE_GMAKE=	yes

cad/iverilog/distinfo

@@ -1,2 +1,2 @@
-SHA256 (verilog-0.9.4.tar.gz) = b4eac7276975cf2d7c2c94246f733dc187feb4d5944034d053c5094279511eb1
-SIZE (verilog-0.9.4.tar.gz) = 1200614
+SHA256 (verilog-0.9.5.tar.gz) = c522b8b873f0cf77003db15c3df0f4a15b738ce4b060d1ca387c88e1b2be185d
+SIZE (verilog-0.9.5.tar.gz) = 1212112

cad/iverilog/pkg-descr

@@ -12,4 +12,4 @@ standard proper is due to be release towards the middle of the
 year 2000. This is a fairly large and complex standard, so it will
 take some time for it to get there, but that's the goal. 
 
-WWW: http://www.icarus.com/eda/verilog/
+WWW: http://iverilog.icarus.com/